<?xml version="1.0" encoding="UTF-8"?>
<testsuites>
	<testsuite name="cvel_test-20260423205414" tests="57" file=".py" time="362.408" timestamp="2026-04-23T21:00:16" failures="0" errors="0" skipped="10">
		<testcase classname="cvel_test" name="test1" time="10.233" timestamp="2026-04-23T20:54:24" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="121">
			<!--Cvel 1: Testing default - expected error-->
		</testcase>
		<testcase classname="cvel_test" name="test10" time="15.818" timestamp="2026-04-23T20:54:40" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="237">
			<!--Cvel10: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...-->
		</testcase>
		<testcase classname="cvel_test" name="test11" time="34.882" timestamp="2026-04-23T20:55:15" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="257">
			<!--Cvel 11: I/O vis set, input vis with two spws, one field selected, 
           2 spws selected, passall = False, regridding 4...-->
		</testcase>
		<testcase classname="cvel_test" name="test12" time="26.341" timestamp="2026-04-23T20:55:41" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="278">
			<!--Cvel 12: Input and output vis set, input vis with two spws, two fields selected, 
           2 spws selected, passall = False, regridding 5...-->
		</testcase>
		<testcase classname="cvel_test" name="test13" time="5.823" timestamp="2026-04-23T20:55:47" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="299">
			<!--Cvel 13: I/O vis set, input vis with one spws, one field selected, one spws selected, 
           passall = False, regridding 6...-->
		</testcase>
		<testcase classname="cvel_test" name="test14" time="0.077" timestamp="2026-04-23T20:55:47" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="321">
			<!--Cvel 14: I/O vis set, input vis with one spws, one field selected, one spws selected, 
           passall = False, non-existing phase center...-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test15" time="11.324" timestamp="2026-04-23T20:55:58" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="346">
			<!--Cvel 15: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 8...-->
		</testcase>
		<testcase classname="cvel_test" name="test16" time="5.960" timestamp="2026-04-23T20:56:04" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="366">
			<!--Cvel 16: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test17" time="9.200" timestamp="2026-04-23T20:56:14" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="386">
			<!--Cvel 17: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test18" time="6.805" timestamp="2026-04-23T20:56:20" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="406">
			<!--Cvel 18: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test2" time="0.032" timestamp="2026-04-23T20:56:20" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="126">
			<!--Cvel 2: Only input vis set - expected error-->
		</testcase>
		<testcase classname="cvel_test" name="test21" time="6.828" timestamp="2026-04-23T20:56:27" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="488">
			<!--Cvel 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test23" time="6.238" timestamp="2026-04-23T20:56:34" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="524">
			<!--Cvel 23: SMA input MS, 24 spws to combine, radio velocity mode, 30 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test25" time="5.275" timestamp="2026-04-23T20:56:39" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="569">
			<!--Cvel 25: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test26" time="5.027" timestamp="2026-04-23T20:56:44" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="594">
			<!--Cvel 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test27" time="6.403" timestamp="2026-04-23T20:56:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="619">
			<!--Cvel 27: SMA input MS, 24 spws to combine, scratch columns, no regridding-->
		</testcase>
		<testcase classname="cvel_test" name="test3" time="0.340" timestamp="2026-04-23T20:56:51" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="133">
			<!--Cvel 3: Input and output vis set-->
		</testcase>
		<testcase classname="cvel_test" name="test30" time="4.580" timestamp="2026-04-23T20:56:55" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="666">
			<!--Cvel 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding-->
		</testcase>
		<testcase classname="cvel_test" name="test31" time="6.318" timestamp="2026-04-23T20:57:01" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="680">
			<!--Cvel 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo-->
		</testcase>
		<testcase classname="cvel_test" name="test32" time="6.053" timestamp="2026-04-23T20:57:08" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="695">
			<!--Cvel 32: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel_test" name="test33" time="6.468" timestamp="2026-04-23T20:57:14" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="711">
			<!--Cvel 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel_test" name="test34" time="7.062" timestamp="2026-04-23T20:57:21" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="727">
			<!--Cvel 34: EVLA high-res input MS, 2 spws to combine-->
		</testcase>
		<testcase classname="cvel_test" name="test35" time="1.136" timestamp="2026-04-23T20:57:22" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="741">
			<!--Cvel 35: test effect of sign of width parameter: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test36" time="1.644" timestamp="2026-04-23T20:57:24" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="761">
			<!--Cvel 36: test effect of sign of width parameter: channel mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test37" time="1.803" timestamp="2026-04-23T20:57:26" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="781">
			<!--Cvel 37: test effect of sign of width parameter: freq mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test38" time="1.452" timestamp="2026-04-23T20:57:27" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="802">
			<!--Cvel 38: test effect of sign of width parameter: freq mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test39" time="0.997" timestamp="2026-04-23T20:57:28" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="823">
			<!--Cvel 39: test effect of sign of width parameter: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test39_veltype_uppercase" time="1.040" timestamp="2026-04-23T20:57:29" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="851">
			<!--Cvel 39: test effect of sign of width parameter: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test4" time="4.796" timestamp="2026-04-23T20:57:34" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="142">
			<!--Cvel 4: I/O vis set, more complex input vis, one field selected-->
		</testcase>
		<testcase classname="cvel_test" name="test40" time="1.563" timestamp="2026-04-23T20:57:35" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="879">
			<!--Cvel 40: test effect of sign of width parameter: radio velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test41" time="1.206" timestamp="2026-04-23T20:57:37" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="907">
			<!--Cvel 41: test effect of sign of width parameter: optical velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test42" time="1.005" timestamp="2026-04-23T20:57:38" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="939">
			<!--Cvel 42: test effect of sign of width parameter: optical velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test46" time="4.258" timestamp="2026-04-23T20:57:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1025">
			<!--Cvel 46: SMA input MS with descending freq, 24 spws, nchan=100-->
		</testcase>
		<testcase classname="cvel_test" name="test48" time="1.187" timestamp="2026-04-23T20:57:43" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1058">
			<!--Cvel 48: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test48_interpolation_uppercase" time="1.408" timestamp="2026-04-23T20:57:45" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1079">
			<!--Cvel 48: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test49" time="0.298" timestamp="2026-04-23T20:57:45" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1100">
			<!--Cvel 49: vopt mode with fftshift, expected error ...-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test5" time="11.424" timestamp="2026-04-23T20:57:56" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="151">
			<!--Cvel 5: I/O vis set, more complex input vis, one field selected, passall = True-->
		</testcase>
		<testcase classname="cvel_test" name="test50" time="17.082" timestamp="2026-04-23T20:58:13" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1120">
			<!--Cvel 50: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test51" time="17.916" timestamp="2026-04-23T20:58:31" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1160">
			<!--Cvel 51: test fftshift regridding: frequency mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test52" time="20.607" timestamp="2026-04-23T20:58:52" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1197">
			<!--Cvel 52: test fftshift regridding: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test53" time="12.431" timestamp="2026-04-23T20:59:04" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1239">
			<!--Cvel 53: cvel of a field with ephemeris attached and outframe SOURCE-->
		</testcase>
		<testcase classname="cvel_test" name="test53_outframe_lowercase" time="12.597" timestamp="2026-04-23T20:59:17" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1252">
			<!--Cvel 53: cvel of a field with ephemeris attached and outframe SOURCE-->
		</testcase>
		<testcase classname="cvel_test" name="test6" time="11.355" timestamp="2026-04-23T20:59:28" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="165">
			<!--Cvel 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True-->
		</testcase>
		<testcase classname="cvel_test" name="test7" time="13.043" timestamp="2026-04-23T20:59:41" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="184">
			<!--Cvel 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False-->
		</testcase>
		<testcase classname="cvel_test" name="test8" time="10.477" timestamp="2026-04-23T20:59:52" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="200">
			<!--Cvel 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 1-->
		</testcase>
		<testcase classname="cvel_test" name="test9" time="24.446" timestamp="2026-04-23T21:00:16" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="218">
			<!--Cvel 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 2-->
		</testcase>
		<testcase classname="cvel_test" name="test_preaveraging_exception" time="0.142" timestamp="2026-04-23T21:00:16" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="428">
			<!-- Cvel pre-averaging exception: check the exception introduced for CAS-9798-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test19" time="0.001" timestamp="2026-04-23T20:56:20" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="452">
			<!--Cvel 19: SMA input MS, 24 spws to combine, channel mode, 10 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test20" time="0.001" timestamp="2026-04-23T20:56:20" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="470">
			<!--Cvel 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test22" time="0.001" timestamp="2026-04-23T20:56:27" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="505">
			<!--Cvel 22: SMA input MS, 24 spws to combine, frequency mode, 210 output channels, negative width-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test24" time="0.001" timestamp="2026-04-23T20:56:34" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="546">
			<!--Cvel 24: SMA input MS, 24 spws to combine, radio velocity mode, 35 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test28" time="0.001" timestamp="2026-04-23T20:56:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="632">
			<!--Cvel 28: SMA input MS, 24 spws to combine, scratch columns, channel mode, 30 channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test29" time="0.001" timestamp="2026-04-23T20:56:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="649">
			<!--Cvel 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test43" time="0.001" timestamp="2026-04-23T20:57:38" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="971">
			<!--Cvel 43: SMA input MS, 1 spw, channel mode, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test44" time="0.001" timestamp="2026-04-23T20:57:38" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="989">
			<!--Cvel 44: SMA input MS, 2 spws to combine, channel mode, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test45" time="0.001" timestamp="2026-04-23T20:57:38" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1007">
			<!--Cvel 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test47" time="0.001" timestamp="2026-04-23T20:57:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1041">
			<!--Cvel 47: SMA input MS with descending freq, 1 spw, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
	</testsuite>
</testsuites>
