<?xml version="1.0" encoding="UTF-8"?>
<testsuites>
	<testsuite name="cvel2_test-20260408195350" tests="60" file=".py" time="102.155" timestamp="2026-04-08T19:55:32" failures="0" errors="0" skipped="0">
		<testcase classname="cvel2_test" name="test1" time="0.022" timestamp="2026-04-08T19:53:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="189">
			<!--cvel2 1: Testing default - expected error-->
			<system-out><![CDATA[Expected error!
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test10" time="2.208" timestamp="2026-04-08T19:53:52" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="375">
			<!--cvel210: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...-->
		</testcase>
		<testcase classname="cvel2_test" name="test11" time="2.226" timestamp="2026-04-08T19:53:54" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="396">
			<!--cvel2 11: I/O vis set, input vis with two spws, one field selected, 
           2 spws selected, passall = False, regridding 4...-->
		</testcase>
		<testcase classname="cvel2_test" name="test11_outframe_uppercase" time="2.220" timestamp="2026-04-08T19:53:57" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="418">
			<!--cvel2 11: I/O vis set, input vis with two spws, one field selected, 
           2 spws selected, passall = False, regridding 4...-->
		</testcase>
		<testcase classname="cvel2_test" name="test12" time="3.866" timestamp="2026-04-08T19:54:00" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="440">
			<!--cvel2 12: Input and output vis set, input vis with two spws, two fields selected, 
           2 spws selected, passall = False, regridding 5...-->
		</testcase>
		<testcase classname="cvel2_test" name="test13" time="0.998" timestamp="2026-04-08T19:54:01" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="462">
			<!--cvel2 13: I/O vis set, input vis with one spw, one field selected, one spw selected, 
           passall = False, regridding 6...-->
		</testcase>
		<testcase classname="cvel2_test" name="test14" time="0.535" timestamp="2026-04-08T19:54:02" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="485">
			<!--cvel2 14: I/O vis set, input vis with one spws, one field selected, one spws selected, 
           passall = False, non-existing phase center...-->
		</testcase>
		<testcase classname="cvel2_test" name="test15" time="1.619" timestamp="2026-04-08T19:54:04" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="511">
			<!--cvel2 15: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 8...-->
		</testcase>
		<testcase classname="cvel2_test" name="test16" time="0.752" timestamp="2026-04-08T19:54:04" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="532">
			<!--cvel2 16: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel2_test" name="test17" time="0.596" timestamp="2026-04-08T19:54:05" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="553">
			<!--cvel2 17: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel2_test" name="test18" time="0.609" timestamp="2026-04-08T19:54:06" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="574">
			<!--cvel2 18: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel2_test" name="test19" time="2.667" timestamp="2026-04-08T19:54:08" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="596">
			<!--cvel2 19: SMA input MS, 24 spws to combine, channel mode, 10 output channels-->
			<system-out><![CDATA[HERE
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test2" time="0.110" timestamp="2026-04-08T19:54:08" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="207">
			<!--cvel2 2: Only input vis set - expected error-->
			<system-out><![CDATA[Expected error!
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test20" time="2.584" timestamp="2026-04-08T19:54:11" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="614">
			<!--cvel2 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test21" time="2.140" timestamp="2026-04-08T19:54:13" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="632">
			<!--cvel2 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test22" time="2.300" timestamp="2026-04-08T19:54:15" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="650">
			<!--cvel2 22: SMA input MS, 24 spws to combine, frequency mode, 210 output channels, negative width-->
		</testcase>
		<testcase classname="cvel2_test" name="test23" time="2.151" timestamp="2026-04-08T19:54:18" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="669">
			<!--cvel2 23: SMA input MS, 24 spws to combine, radio velocity mode, 30 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test24" time="2.143" timestamp="2026-04-08T19:54:20" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="692">
			<!--cvel2 24: SMA input MS, 24 spws to combine, radio velocity mode, 35 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test25" time="2.602" timestamp="2026-04-08T19:54:22" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="715">
			<!--cvel2 25: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test25_veltype_uppercase" time="2.488" timestamp="2026-04-08T19:54:25" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="741">
			<!--cvel2 25: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test26" time="2.755" timestamp="2026-04-08T19:54:28" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="767">
			<!--cvel2 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test27" time="2.492" timestamp="2026-04-08T19:54:30" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="793">
			<!--cvel2 27: SMA input MS, 24 spws to combine, scratch columns, no regridding-->
		</testcase>
		<testcase classname="cvel2_test" name="test28" time="2.297" timestamp="2026-04-08T19:54:32" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="807">
			<!--cvel2 28: SMA input MS, 24 spws to combine, scratch columns, channel mode, 30 channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test29" time="2.355" timestamp="2026-04-08T19:54:35" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="824">
			<!--cvel2 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels-->
		</testcase>
		<testcase classname="cvel2_test" name="test3" time="1.221" timestamp="2026-04-08T19:54:36" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="225">
			<!--cvel2 3: Input and output vis set-->
		</testcase>
		<testcase classname="cvel2_test" name="test30" time="2.821" timestamp="2026-04-08T19:54:39" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="841">
			<!--cvel2 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding-->
		</testcase>
		<testcase classname="cvel2_test" name="test31" time="2.591" timestamp="2026-04-08T19:54:41" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="856">
			<!--cvel2 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo-->
		</testcase>
		<testcase classname="cvel2_test" name="test32" time="2.478" timestamp="2026-04-08T19:54:44" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="872">
			<!--cvel2 32: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel2_test" name="test33" time="0.523" timestamp="2026-04-08T19:54:44" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="889">
			<!--cvel2 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel2_test" name="test34" time="5.033" timestamp="2026-04-08T19:54:49" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="906">
			<!--cvel2 34: EVLA high-res input MS, 2 spws to combine-->
		</testcase>
		<testcase classname="cvel2_test" name="test35" time="1.392" timestamp="2026-04-08T19:54:51" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="935">
			<!--cvel2 35: test effect of sign of width parameter: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test36" time="1.112" timestamp="2026-04-08T19:54:52" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="956">
			<!--cvel2 36: test effect of sign of width parameter: channel mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test37" time="1.355" timestamp="2026-04-08T19:54:53" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="977">
			<!--cvel2 37: test effect of sign of width parameter: freq mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test38" time="1.317" timestamp="2026-04-08T19:54:54" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="999">
			<!--cvel2 38: test effect of sign of width parameter: freq mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test39" time="1.300" timestamp="2026-04-08T19:54:56" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1021">
			<!--cvel2 39: test effect of sign of width parameter: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test4" time="0.418" timestamp="2026-04-08T19:54:56" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="235">
			<!--cvel2 4: I/O vis set, more Tableslex input vis, one field selected-->
		</testcase>
		<testcase classname="cvel2_test" name="test40" time="1.288" timestamp="2026-04-08T19:54:58" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1050">
			<!--cvel2 40: test effect of sign of width parameter: radio velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test41" time="1.218" timestamp="2026-04-08T19:54:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1079">
			<!--cvel2 41: test effect of sign of width parameter: optical velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test42" time="1.245" timestamp="2026-04-08T19:55:00" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1112">
			<!--cvel2 42: test effect of sign of width parameter: optical velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test43" time="0.500" timestamp="2026-04-08T19:55:00" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1165">
			<!--cvel2 43: SMA input MS, 1 spw, channel mode, nchan not set-->
		</testcase>
		<testcase classname="cvel2_test" name="test44" time="0.599" timestamp="2026-04-08T19:55:01" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1183">
			<!--cvel2 44: SMA input MS, 2 spws to combine, channel mode, nchan not set-->
		</testcase>
		<testcase classname="cvel2_test" name="test45" time="0.570" timestamp="2026-04-08T19:55:02" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1201">
			<!--cvel2 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width-->
		</testcase>
		<testcase classname="cvel2_test" name="test46" time="1.718" timestamp="2026-04-08T19:55:03" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1219">
			<!--cvel2 46: SMA input MS with descending freq, 24 spws, nchan=100-->
		</testcase>
		<testcase classname="cvel2_test" name="test47" time="0.358" timestamp="2026-04-08T19:55:04" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1236">
			<!--cvel2 47: SMA input MS with descending freq, 1 spw, nchan not set-->
		</testcase>
		<testcase classname="cvel2_test" name="test48" time="1.276" timestamp="2026-04-08T19:55:05" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1253">
			<!--cvel2 48: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test49" time="1.437" timestamp="2026-04-08T19:55:06" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1275">
			<!--cvel2 49: vopt mode with fftshift, expected error ...-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test5" time="0.429" timestamp="2026-04-08T19:55:07" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="245">
			<!--cvel2 5: I/O vis set, more complex input vis, one field selected, passall = True-->
		</testcase>
		<testcase classname="cvel2_test" name="test50" time="1.228" timestamp="2026-04-08T19:55:08" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1296">
			<!--cvel2 50: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test51" time="1.122" timestamp="2026-04-08T19:55:09" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1337">
			<!--cvel2 51: test fftshift regridding: frequency mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test52" time="1.449" timestamp="2026-04-08T19:55:11" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1375">
			<!--cvel2 52: test fftshift regridding: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test53" time="2.830" timestamp="2026-04-08T19:55:13" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1417">
			<!--cvel2 53: cvel2 of a field with ephemeris attached and outframe SOURCE-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test6" time="2.215" timestamp="2026-04-08T19:55:16" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="260">
			<!--cvel2 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True-->
		</testcase>
		<testcase classname="cvel2_test" name="test6_datacolumn_uppercase" time="1.885" timestamp="2026-04-08T19:55:18" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="288">
			<!--cvel2 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True-->
		</testcase>
		<testcase classname="cvel2_test" name="test7" time="1.654" timestamp="2026-04-08T19:55:19" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="319">
			<!--cvel2 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False-->
		</testcase>
		<testcase classname="cvel2_test" name="test8" time="1.605" timestamp="2026-04-08T19:55:21" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="336">
			<!--cvel2 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 1-->
		</testcase>
		<testcase classname="cvel2_test" name="test9" time="2.260" timestamp="2026-04-08T19:55:23" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="355">
			<!--cvel2 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 2-->
		</testcase>
		<testcase classname="cvel2_test" name="test_mms_heuristics1" time="1.608" timestamp="2026-04-08T19:55:25" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1435">
			<!--cvel2 : MMS heuristic tests-->
			<system-out><![CDATA[................. Creating test MMS ..................
Expected error!
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test_mms_heuristics2" time="3.080" timestamp="2026-04-08T19:55:28" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1455">
			<!--cvel2 : MMS heuristic tests-->
			<system-out><![CDATA[................. Creating test MMS ..................
Expected error!
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test_mms_heuristics3" time="3.803" timestamp="2026-04-08T19:55:32" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1475">
			<!--cvel2 : MMS heuristic tests-->
			<system-out><![CDATA[................. Creating test MMS ..................
]]></system-out>
		</testcase>
		<testcase classname="cvel2_test" name="test_preaveraging_exception" time="0.486" timestamp="2026-04-08T19:55:32" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel2_casashell.py" line="1145">
			<!-- cvel2 pre-averaging exception not there any longer: check the exception
        introduced for CAS-9798, but removed after CAS-9853.-->
		</testcase>
	</testsuite>
</testsuites>
