Line data Source code
1 : *=======================================================================
2 : * These are a set of byte-oriented routines to facilitate conversion
3 : * of data between different architectures. They are designed to work
4 : * on any architecture which uses two's complement byte arithmetic.
5 : *
6 : * IB2B: Big-endian integer -> big-endian integer (copy).
7 : * IB2L: big-endian integer -> little-endian integer (byte swap).
8 : * IB2V: big-endian integer -> VAX integer (byte swap).
9 : *
10 : * IL2B: little-endian integer -> big-endian integer (byte swap).
11 : * IL2L: little-endian integer -> little-endian integer (copy).
12 : * IL2V: little-endian integer -> VAX integer (copy).
13 : *
14 : * IV2B: VAX integer -> big-endian integer (byte swap).
15 : * IV2L: VAX integer -> little-endian integer (copy).
16 : * IV2V: VAX integer -> VAX integer (copy).
17 : *
18 : * RB2B: IEEE big-endian real -> IEEE big-endian real (copy).
19 : * RB2L: IEEE big-endian real -> IEEE little-endian real (byte swap).
20 : * RB2V: IEEE big-endian real -> VAX real (format translation).
21 : *
22 : * RL2B: IEEE little-endian real -> IEEE big-endian real (byte swap).
23 : * RL2L: IEEE little-endian real -> IEEE little-endian real (copy).
24 : * RL2V: IEEE little-endian real -> VAX real (format translation).
25 : *
26 : * RV2B: VAX real -> IEEE big-endian real (format translation).
27 : * RV2L: VAX real -> IEEE little-endian real (format translation).
28 : * RV2V: VAX real -> VAX real (copy).
29 : *
30 : * The routines take two BYTE(4) dummy arguments, the first being the
31 : * given value-to-convert and the second being the returned, converted
32 : * value. They may be called with INTEGER or REAL actual arguments in
33 : * place of the BYTE(4) dummy arguments, and the arguments may have the
34 : * same address, e.g. CALL IV2B (B, B) is allowed.
35 : *
36 : * Original: 1997/08/20 MRC
37 : * $Id: dconv.f,v 1.6 2007/05/04 02:27:54 cal103 Exp $
38 : *=======================================================================
39 : * Two's complement integer representation
40 : *-----------------------------------------------------------------------
41 : *
42 : * The one's complement of a bit pattern is formed by interchanging
43 : * zeros and ones. For example:
44 : *
45 : * Binary pattern: 00110010
46 : * One's complement: 11001101
47 : *
48 : * In two's complement arithmetic, negative integers are represented
49 : * as the one's complement plus 1. For a one-byte signed integer
50 : *
51 : * Binary 1: 00000001
52 : * Two's complement -1: 11111111
53 : *
54 : * When a binary integer is added to its two's complement the result
55 : * is all zeros (binary 0) with the carry bit set (ignored).
56 : *
57 : * Note the special case:
58 : *
59 : * Binary pattern: 10000000
60 : * Two's complement: 10000000
61 : *
62 : * This is taken to be the least negative integer, so the range for
63 : * one-byte signed integers is -128 to +127. Similarly for multi-byte
64 : * integers.
65 : *
66 : * All modern computers (including VAXs) use two's complement integer
67 : * representation. For four-byte integers
68 : *
69 : * byte: 0 1 2 3
70 : * siiiiiii iiiiiiii iiiiiiii iiiiiiii
71 : * ^ ^
72 : * bit: 31 0
73 : *
74 : * These byte and bit numbers DO NOT reflect the order in memory, see
75 : * below.
76 : *
77 : * Bit 31 is the sign bit and significance increases with increasing
78 : * bit number.
79 : *
80 : * The "storage format" is commonly "big-endian" or "little-endian":
81 : *
82 : * Byte addresses in memory
83 : * Storage format b b+1 b+2 b+3
84 : * -------------- -----------------------------
85 : * Big-endian 0 1 2 3
86 : * Little-endian 3 2 1 0
87 : *
88 : * Where b is the byte address in memory (b precedes b+1). DEC (VAX,
89 : * Alpha) and INTEL machines (PCs) are little-endian while most others
90 : * are big-endian.
91 : *
92 : *=======================================================================
93 : * IEEE 754-1985 single-precision floating representation
94 : *-----------------------------------------------------------------------
95 : *
96 : * The bit-pattern of an IEEE 754-1985 single-precision floating point
97 : * number is
98 : *
99 : * byte: 0 1 2 3
100 : * seeeeeee efffffff ffffffff ffffffff
101 : * ^ ^
102 : * bit: 31 0
103 : *
104 : * These byte and bit numbers DO NOT reflect the order in memory, see
105 : * below.
106 : *
107 : * bit field (significance increases with increasing bit number)
108 : * ---------
109 : * 31 sign bit ( 1 bit)
110 : * 23-30 exponent ( 8 bits)
111 : * 0-22 fraction (23 bits)
112 : *
113 : * The IEEE single-precision representation is summarized as follows:
114 : *
115 : * seeeeeee efffffff ffffffff ffffffff
116 : * -----------------------------------
117 : * 00000000 00000000 00000000 00000000 +0
118 : * 10000000 00000000 00000000 00000000 -0
119 : * 0 < e < 255 Normalized number
120 : * e = 0, f != 0 Unnormalized number
121 : * 01111111 10000000 00000000 00000000 +Infinity
122 : * 11111111 10000000 00000000 00000000 -Infinity
123 : * s1111111 11ffffff ffffffff ffffffff Quiet NaN
124 : * s1111111 10ffffff ffffffff ffffffff Signalling NaN (f != 0)
125 : *
126 : * The value of a normalized number is
127 : *
128 : * (-1)**s * 2**(e-127) * 1.f
129 : *
130 : * where the implicit fraction bit occurs to the left of the binary
131 : * radix point.
132 : *
133 : * The value of an unnormalized number is
134 : *
135 : * (-1)**s * 2**(-126) * 0.f
136 : *
137 : * Unnormalized numbers allow for "progressive underflow".
138 : *
139 : * The IEEE 754-1985 standard explicitly does not specify a "storage
140 : * format", byte ordering is commonly "big-endian" or "little-endian":
141 : *
142 : * Byte addresses in memory
143 : * Storage format b b+1 b+2 b+3
144 : * -------------- -----------------------------
145 : * Big-endian 0 1 2 3
146 : * Little-endian 3 2 1 0
147 : *
148 : * Where b is the byte address in memory (b precedes b+1). DEC Alphas,
149 : * and INTEL machines (PCs) are commonly little-endian, while most
150 : * other IEEE 754 machines are big-endian.
151 : *
152 : *=======================================================================
153 : * Integer representations of IEEE floating point infinities and NaNs
154 : *-----------------------------------------------------------------------
155 : *
156 : * Assuming consistent endianness of integer and single-precision
157 : * representations the following relations may be useful:
158 : *
159 : * -Infinity:
160 : * 11111111 10000000 00000000 00000000 = -8388608
161 : *
162 : * Negative range of signalling NaNs:
163 : * 11111111 10000000 00000000 00000001 = -8388607
164 : * :
165 : * 11111111 10111111 11111111 11111111 = -4194305
166 : *
167 : * Negative range of quiet NaNs:
168 : * 11111111 11000000 00000000 00000000 = -4194304
169 : * :
170 : * 11111111 11111111 11111111 11111111 = -1
171 : *
172 : * +Infinity:
173 : * 01111111 10000000 00000000 00000000 = 2139095040
174 : *
175 : * Positive range of signalling NaNs:
176 : * 01111111 10000000 00000000 00000001 = 2139095041
177 : * :
178 : * 01111111 10111111 11111111 11111111 = 2143289343
179 : *
180 : * Positive range of quiet NaNs:
181 : * 01111111 11000000 00000000 00000000 = 2143289344
182 : * :
183 : * 01111111 11111111 11111111 11111111 = 2147483647
184 : *
185 : * Thus the integer representation of IEEE floating point infinities
186 : * and NaNs ranges from -8388608 to -1, and 2139095040 to 2147483647
187 : * inclusive.
188 : *
189 : *=======================================================================
190 : * IEEE 754-1985 double-precision floating representation
191 : *-----------------------------------------------------------------------
192 : *
193 : * The bit-pattern of an IEEE 754-1985 double-precision floating point
194 : * number is
195 : *
196 : * byte: 0 1 2 3 4 ... 7
197 : * seeeeeee eeeeffff ffffffff ffffffff ffffffff ... ffffffff
198 : * ^ ^
199 : * bit: 63 0
200 : *
201 : * bit field (significance increases with increasing bit number)
202 : * ---------
203 : * 63 sign bit ( 1 bit)
204 : * 52-62 exponent (11 bits)
205 : * 0-51 fraction (52 bits)
206 : *
207 : * The representation of infinities and NaNs follows the pattern
208 : * established for single-precision numbers.
209 : *
210 : * The value of a normalized number is
211 : *
212 : * (-1)**s * 2**(e-1023) * 1.f
213 : *
214 : * where the implicit fraction bit occurs to the left of the binary
215 : * radix point.
216 : *
217 : * The value of an unnormalized number is
218 : *
219 : * (-1)**s * 2**(-1022) * 0.f
220 : *
221 : *=======================================================================
222 : * VAX F_floating single-precision floating representation
223 : *-----------------------------------------------------------------------
224 : *
225 : * VAX F_floating format does not follow the IEEE 754 standard. The
226 : * bit pattern is
227 : *
228 : * byte: 0 1 2 3
229 : * seeeeeee efffffff ffffffff ffffffff
230 : * ^ ^
231 : * bit: 31 0
232 : *
233 : * These byte and bit numbers DO NOT reflect the order in memory, see
234 : * below.
235 : *
236 : * bit field (significance increases with increasing bit number)
237 : * ---------
238 : * 31 sign bit
239 : * 23-30 exponent
240 : * 0-22 fraction
241 : *
242 : * The VAX F_floating representation is summarized as follows:
243 : *
244 : * seeeeeee efffffff ffffffff ffffffff
245 : * -----------------------------------
246 : * 00000000 0fffffff ffffffff ffffffff 0 (unsigned)
247 : * 10000000 0fffffff ffffffff ffffffff reserved operand
248 : * 0 < e <= 255 Normal number
249 : *
250 : * The value of a normal number is
251 : *
252 : * (-1)**s * 2**(e-128) * 0.1f
253 : *
254 : * where the implicit fraction bit occurs to the right of the binary
255 : * radix point.
256 : *
257 : * Byte addresses in memory
258 : * Storage format b b+1 b+2 b+3
259 : * -------------- -----------------------------
260 : * VAX F_floating 1 0 3 2
261 : *
262 : * The address of a VAX F_floating datum is the address, b, of byte 1.
263 : *
264 : *-----------------------------------------------------------------------
265 : *
266 : * Apart from byte ordering, normal IEEE 754 numbers differ from VAX
267 : * F_floating numbers by a factor of 4 because:
268 : *
269 : * * IEEE exponents are excess 127 whereas VAX exponents are excess
270 : * 128.
271 : *
272 : * * The IEEE implicit fraction bit occurs to the left of the binary
273 : * radix point wheras the VAX implicit bit occurs to the right.
274 : *
275 : * The multiplication or division by 4 can be accomplished by adding
276 : * or subtracting 1 from byte 0.
277 : *
278 : *=======================================================================
279 :
280 :
281 :
282 0 : SUBROUTINE BCOPY (B1, B2)
283 : *-----------------------------------------------------------------------
284 : * Does byte copying 0123 <--> 0123.
285 : *-----------------------------------------------------------------------
286 : BYTE B1(0:3), B2(0:3)
287 : *-----------------------------------------------------------------------
288 : * Copy big-endian integer --> big-endian integer.
289 0 : ENTRY IB2B (B1, B2)
290 :
291 : * Copy little-endian integer --> little-endian integer.
292 0 : ENTRY IL2L (B1, B2)
293 :
294 : * Copy VAX integer --> VAX integer.
295 0 : ENTRY IV2V (B1, B2)
296 : *-----------------------------------------------------------------------
297 : * Copy VAX integer --> little-endian integer.
298 0 : ENTRY IV2L (B1, B2)
299 :
300 : * Copy little-endian integer --> VAX integer.
301 0 : ENTRY IL2V (B1, B2)
302 : *-----------------------------------------------------------------------
303 : * Copy IEEE big-endian real --> IEEE big-endian real.
304 0 : ENTRY RB2B (B1, B2)
305 :
306 : * Copy IEEE little-endian real --> IEEE little-endian real.
307 0 : ENTRY RL2L (B1, B2)
308 :
309 : * Copy VAX real --> VAX real.
310 0 : ENTRY RV2V (B1, B2)
311 : *-----------------------------------------------------------------------
312 0 : B2(0) = B1(0)
313 0 : B2(1) = B1(1)
314 0 : B2(2) = B1(2)
315 0 : B2(3) = B1(3)
316 :
317 0 : RETURN
318 : END
319 :
320 :
321 :
322 0 : SUBROUTINE BSWAP (B1, B2)
323 : *-----------------------------------------------------------------------
324 : * Does byte swapping 0123 <--> 3210.
325 : *-----------------------------------------------------------------------
326 : BYTE B(0:3), B1(0:3), B2(0:3)
327 : *-----------------------------------------------------------------------
328 : * Convert VAX integer --> big-endian integer.
329 0 : ENTRY IV2B (B1, B2)
330 :
331 : * Convert big-endian integer --> VAX integer.
332 0 : ENTRY IB2V (B1, B2)
333 : *-----------------------------------------------------------------------
334 : * Convert little-endian integer --> big-endian integer.
335 0 : ENTRY IL2B (B1, B2)
336 :
337 : * Convert big-endian integer --> little-endian integer.
338 0 : ENTRY IB2L (B1, B2)
339 : *-----------------------------------------------------------------------
340 : * Convert IEEE little-endian real --> IEEE big-endian real.
341 0 : ENTRY RL2B (B1, B2)
342 :
343 : * Convert IEEE big-endian real --> IEEE little-endian real.
344 0 : ENTRY RB2L (B1, B2)
345 : *-----------------------------------------------------------------------
346 0 : B(0) = B1(3)
347 0 : B(1) = B1(2)
348 0 : B(2) = B1(1)
349 0 : B(3) = B1(0)
350 :
351 0 : B2(0) = B(0)
352 0 : B2(1) = B(1)
353 0 : B2(2) = B(2)
354 0 : B2(3) = B(3)
355 :
356 0 : RETURN
357 : END
358 :
359 :
360 :
361 0 : SUBROUTINE RV2B (B1, B2)
362 : *-----------------------------------------------------------------------
363 : * Converts VAX real --> IEEE big-endian real.
364 : *-----------------------------------------------------------------------
365 : BYTE B(0:3), B1(0:3), B2(0:3)
366 : *-----------------------------------------------------------------------
367 : * Natural order.
368 0 : B(0) = B1(1)
369 0 : B(1) = B1(0)
370 0 : B(2) = B1(3)
371 0 : B(3) = B1(2)
372 :
373 0 : IF (B(0).EQ.-128 .AND. B(1).GE.0) THEN
374 : * VAX reserved operand, set to NaN.
375 0 : B(0) = -1
376 0 : B(1) = -1
377 0 : B(2) = 0
378 0 : B(3) = 0
379 :
380 0 : ELSE IF (B(1).LT.0 .AND. (B(0).EQ.127 .OR. B(0).EQ.-1)) THEN
381 : * Overflow, set to signed infinity.
382 : * B(0) = B(0)
383 0 : B(1) = -128
384 0 : B(2) = 0
385 0 : B(3) = 0
386 :
387 0 : ELSE IF (B(0).EQ.0 .AND. B(1).GE.0) THEN
388 : * VAX zero.
389 0 : B(0) = 0
390 0 : B(1) = 0
391 0 : B(2) = 0
392 0 : B(3) = 0
393 :
394 : ELSE
395 : * Scale VAX to IEEE.
396 0 : B(0) = B(0) - 1
397 : END IF
398 :
399 : * Big-endian ordering.
400 0 : B2(0) = B(0)
401 0 : B2(1) = B(1)
402 0 : B2(2) = B(2)
403 0 : B2(3) = B(3)
404 :
405 0 : RETURN
406 : END
407 :
408 :
409 :
410 0 : SUBROUTINE RB2V (B1, B2)
411 : *-----------------------------------------------------------------------
412 : * Converts IEEE big-endian real --> VAX real.
413 : *-----------------------------------------------------------------------
414 : BYTE B(0:3), B1(0:3), B2(0:3)
415 : *-----------------------------------------------------------------------
416 : * Natural ordering.
417 0 : B(0) = B1(0)
418 0 : B(1) = B1(1)
419 0 : B(2) = B1(2)
420 0 : B(3) = B1(3)
421 :
422 0 : IF (B(1).LT.0 .AND. (B(0).EQ.127 .OR. B(0).EQ.-1)) THEN
423 : * Convert IEEE NaN or Infinity to VAX reserved operand.
424 0 : B(0) = -128
425 0 : B(1) = 0
426 0 : B(2) = 0
427 0 : B(3) = 0
428 :
429 0 : ELSE IF (B(0).EQ.-128 .AND. B(1).GE.0) THEN
430 : * Convert IEEE negative zero or unnormalized number to VAX zero.
431 0 : B(0) = 0
432 0 : B(1) = 0
433 0 : B(2) = 0
434 0 : B(3) = 0
435 :
436 : ELSE
437 : * Scale IEEE to VAX.
438 0 : B(0) = B(0) + 1
439 : END IF
440 :
441 : * VAX ordering.
442 0 : B2(0) = B(1)
443 0 : B2(1) = B(0)
444 0 : B2(2) = B(3)
445 0 : B2(3) = B(2)
446 :
447 0 : RETURN
448 : END
449 :
450 :
451 :
452 0 : SUBROUTINE RV2L (B1, B2)
453 : *-----------------------------------------------------------------------
454 : * Converts VAX real --> IEEE little-endian real.
455 : *-----------------------------------------------------------------------
456 : BYTE B(0:3), B1(0:3), B2(0:3)
457 : *-----------------------------------------------------------------------
458 : * Natural order.
459 0 : B(0) = B1(1)
460 0 : B(1) = B1(0)
461 0 : B(2) = B1(3)
462 0 : B(3) = B1(2)
463 :
464 0 : IF (B(0).EQ.-128 .AND. B(1).GE.0) THEN
465 : * VAX reserved operand, set to NaN.
466 0 : B(0) = -1
467 0 : B(1) = -1
468 0 : B(2) = 0
469 0 : B(3) = 0
470 :
471 0 : ELSE IF (B(1).LT.0 .AND. (B(0).EQ.127 .OR. B(0).EQ.-1)) THEN
472 : * Overflow, set to signed infinity.
473 : * B(0) = B(0)
474 0 : B(1) = -128
475 0 : B(2) = 0
476 0 : B(3) = 0
477 :
478 0 : ELSE IF (B(0).EQ.0 .AND. B(1).GE.0) THEN
479 : * VAX zero.
480 0 : B(0) = 0
481 0 : B(1) = 0
482 0 : B(2) = 0
483 0 : B(3) = 0
484 :
485 : ELSE
486 : * Scale VAX to IEEE.
487 0 : B(0) = B(0) - 1
488 : END IF
489 :
490 : * Little-endian ordering.
491 0 : B2(0) = B(3)
492 0 : B2(1) = B(2)
493 0 : B2(2) = B(1)
494 0 : B2(3) = B(0)
495 :
496 0 : RETURN
497 : END
498 :
499 :
500 :
501 0 : SUBROUTINE RL2V (B1, B2)
502 : *-----------------------------------------------------------------------
503 : * Converts IEEE little-endian real --> VAX real.
504 : *-----------------------------------------------------------------------
505 : BYTE B(0:3), B1(0:3), B2(0:3)
506 : *-----------------------------------------------------------------------
507 : * Natural order.
508 0 : B(0) = B1(3)
509 0 : B(1) = B1(2)
510 0 : B(2) = B1(1)
511 0 : B(3) = B1(0)
512 :
513 0 : IF (B(1).LT.0 .AND. (B(0).EQ.127 .OR. B(0).EQ.-1)) THEN
514 : * Convert IEEE NaN or Infinity to VAX reserved operand.
515 0 : B(0) = -128
516 0 : B(1) = 0
517 0 : B(2) = 0
518 0 : B(3) = 0
519 :
520 0 : ELSE IF (B(0).EQ.-128 .AND. B(1).GE.0) THEN
521 : * Convert IEEE negative zero or unnormalized number to VAX zero.
522 0 : B(0) = 0
523 0 : B(1) = 0
524 0 : B(2) = 0
525 0 : B(3) = 0
526 :
527 : ELSE
528 : * Scale IEEE to VAX.
529 0 : B(0) = B(0) + 1
530 : END IF
531 :
532 : * VAX ordering.
533 0 : B2(0) = B(1)
534 0 : B2(1) = B(0)
535 0 : B2(2) = B(3)
536 0 : B2(3) = B(2)
537 :
538 0 : RETURN
539 : END
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