<?xml version="1.0" encoding="UTF-8"?>
<testsuites>
	<testsuite name="cvel_test-20260923182723" tests="57" file=".py" time="163.084" timestamp="2026-09-23T18:30:06" failures="0" errors="0" skipped="10">
		<testcase classname="cvel_test" name="test1" time="6.593" timestamp="2026-09-23T18:27:30" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="122">
			<!--Cvel 1: Testing default - expected error-->
		</testcase>
		<testcase classname="cvel_test" name="test10" time="7.258" timestamp="2026-09-23T18:27:37" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="238">
			<!--Cvel10: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...-->
		</testcase>
		<testcase classname="cvel_test" name="test11" time="23.168" timestamp="2026-09-23T18:28:00" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="258">
			<!--Cvel 11: I/O vis set, input vis with two spws, one field selected, 
           2 spws selected, passall = False, regridding 4...-->
		</testcase>
		<testcase classname="cvel_test" name="test12" time="17.933" timestamp="2026-09-23T18:28:18" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="279">
			<!--Cvel 12: Input and output vis set, input vis with two spws, two fields selected, 
           2 spws selected, passall = False, regridding 5...-->
		</testcase>
		<testcase classname="cvel_test" name="test13" time="0.886" timestamp="2026-09-23T18:28:19" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="300">
			<!--Cvel 13: I/O vis set, input vis with one spws, one field selected, one spws selected, 
           passall = False, regridding 6...-->
		</testcase>
		<testcase classname="cvel_test" name="test14" time="0.056" timestamp="2026-09-23T18:28:19" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="322">
			<!--Cvel 14: I/O vis set, input vis with one spws, one field selected, one spws selected, 
           passall = False, non-existing phase center...-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test15" time="5.504" timestamp="2026-09-23T18:28:25" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="347">
			<!--Cvel 15: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 8...-->
		</testcase>
		<testcase classname="cvel_test" name="test16" time="1.306" timestamp="2026-09-23T18:28:26" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="367">
			<!--Cvel 16: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test17" time="1.361" timestamp="2026-09-23T18:28:27" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="387">
			<!--Cvel 17: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test18" time="1.357" timestamp="2026-09-23T18:28:29" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="407">
			<!--Cvel 18: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...-->
		</testcase>
		<testcase classname="cvel_test" name="test2" time="0.022" timestamp="2026-09-23T18:28:29" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="127">
			<!--Cvel 2: Only input vis set - expected error-->
		</testcase>
		<testcase classname="cvel_test" name="test21" time="2.604" timestamp="2026-09-23T18:28:31" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="489">
			<!--Cvel 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test23" time="2.498" timestamp="2026-09-23T18:28:34" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="525">
			<!--Cvel 23: SMA input MS, 24 spws to combine, radio velocity mode, 30 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test25" time="2.506" timestamp="2026-09-23T18:28:36" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="570">
			<!--Cvel 25: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test26" time="2.552" timestamp="2026-09-23T18:28:39" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="595">
			<!--Cvel 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels-->
		</testcase>
		<testcase classname="cvel_test" name="test27" time="2.876" timestamp="2026-09-23T18:28:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="620">
			<!--Cvel 27: SMA input MS, 24 spws to combine, scratch columns, no regridding-->
		</testcase>
		<testcase classname="cvel_test" name="test3" time="0.125" timestamp="2026-09-23T18:28:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="134">
			<!--Cvel 3: Input and output vis set-->
		</testcase>
		<testcase classname="cvel_test" name="test30" time="2.401" timestamp="2026-09-23T18:28:44" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="667">
			<!--Cvel 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding-->
		</testcase>
		<testcase classname="cvel_test" name="test31" time="3.070" timestamp="2026-09-23T18:28:47" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="681">
			<!--Cvel 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo-->
		</testcase>
		<testcase classname="cvel_test" name="test32" time="3.169" timestamp="2026-09-23T18:28:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="696">
			<!--Cvel 32: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel_test" name="test33" time="0.468" timestamp="2026-09-23T18:28:51" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="712">
			<!--Cvel 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing-->
		</testcase>
		<testcase classname="cvel_test" name="test34" time="4.658" timestamp="2026-09-23T18:28:55" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="728">
			<!--Cvel 34: EVLA high-res input MS, 2 spws to combine-->
		</testcase>
		<testcase classname="cvel_test" name="test35" time="0.370" timestamp="2026-09-23T18:28:56" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="742">
			<!--Cvel 35: test effect of sign of width parameter: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test36" time="0.339" timestamp="2026-09-23T18:28:56" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="762">
			<!--Cvel 36: test effect of sign of width parameter: channel mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test37" time="0.330" timestamp="2026-09-23T18:28:57" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="782">
			<!--Cvel 37: test effect of sign of width parameter: freq mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test38" time="0.398" timestamp="2026-09-23T18:28:57" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="803">
			<!--Cvel 38: test effect of sign of width parameter: freq mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test39" time="0.361" timestamp="2026-09-23T18:28:57" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="824">
			<!--Cvel 39: test effect of sign of width parameter: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test39_veltype_uppercase" time="0.370" timestamp="2026-09-23T18:28:58" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="852">
			<!--Cvel 39: test effect of sign of width parameter: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test4" time="0.502" timestamp="2026-09-23T18:28:58" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="143">
			<!--Cvel 4: I/O vis set, more complex input vis, one field selected-->
		</testcase>
		<testcase classname="cvel_test" name="test40" time="0.366" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="880">
			<!--Cvel 40: test effect of sign of width parameter: radio velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test41" time="0.364" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="908">
			<!--Cvel 41: test effect of sign of width parameter: optical velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test42" time="0.332" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="940">
			<!--Cvel 42: test effect of sign of width parameter: optical velocity mode, width negative-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test46" time="1.901" timestamp="2026-09-23T18:29:01" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1026">
			<!--Cvel 46: SMA input MS with descending freq, 24 spws, nchan=100-->
		</testcase>
		<testcase classname="cvel_test" name="test48" time="0.384" timestamp="2026-09-23T18:29:02" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1059">
			<!--Cvel 48: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test48_interpolation_uppercase" time="0.405" timestamp="2026-09-23T18:29:02" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1080">
			<!--Cvel 48: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test49" time="0.118" timestamp="2026-09-23T18:29:02" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1101">
			<!--Cvel 49: vopt mode with fftshift, expected error ...-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test5" time="1.320" timestamp="2026-09-23T18:29:03" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="152">
			<!--Cvel 5: I/O vis set, more complex input vis, one field selected, passall = True-->
		</testcase>
		<testcase classname="cvel_test" name="test50" time="2.458" timestamp="2026-09-23T18:29:06" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1121">
			<!--Cvel 50: test fftshift regridding: channel mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test51" time="2.176" timestamp="2026-09-23T18:29:08" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1161">
			<!--Cvel 51: test fftshift regridding: frequency mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test52" time="2.033" timestamp="2026-09-23T18:29:10" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1198">
			<!--Cvel 52: test fftshift regridding: radio velocity mode, width positive-->
			<system-out><![CDATA[Testing channel frequencies ...
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test53" time="15.124" timestamp="2026-09-23T18:29:25" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1240">
			<!--Cvel 53: cvel of a field with ephemeris attached and outframe SOURCE-->
		</testcase>
		<testcase classname="cvel_test" name="test53_outframe_lowercase" time="14.954" timestamp="2026-09-23T18:29:40" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1253">
			<!--Cvel 53: cvel of a field with ephemeris attached and outframe SOURCE-->
		</testcase>
		<testcase classname="cvel_test" name="test6" time="1.425" timestamp="2026-09-23T18:29:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="166">
			<!--Cvel 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True-->
		</testcase>
		<testcase classname="cvel_test" name="test7" time="5.345" timestamp="2026-09-23T18:29:47" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="185">
			<!--Cvel 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False-->
		</testcase>
		<testcase classname="cvel_test" name="test8" time="3.409" timestamp="2026-09-23T18:29:50" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="201">
			<!--Cvel 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 1-->
		</testcase>
		<testcase classname="cvel_test" name="test9" time="15.816" timestamp="2026-09-23T18:30:06" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="219">
			<!--Cvel 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 
           passall = False, regridding 2-->
		</testcase>
		<testcase classname="cvel_test" name="test_preaveraging_exception" time="0.107" timestamp="2026-09-23T18:30:06" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="429">
			<!-- Cvel pre-averaging exception: check the exception introduced for CAS-9798-->
			<system-out><![CDATA[*** Expected error ***
]]></system-out>
		</testcase>
		<testcase classname="cvel_test" name="test19" time="0.000" timestamp="2026-09-23T18:28:29" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="453">
			<!--Cvel 19: SMA input MS, 24 spws to combine, channel mode, 10 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test20" time="0.000" timestamp="2026-09-23T18:28:29" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="471">
			<!--Cvel 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test22" time="0.001" timestamp="2026-09-23T18:28:31" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="506">
			<!--Cvel 22: SMA input MS, 24 spws to combine, frequency mode, 210 output channels, negative width-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test24" time="0.001" timestamp="2026-09-23T18:28:34" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="547">
			<!--Cvel 24: SMA input MS, 24 spws to combine, radio velocity mode, 35 output channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test28" time="0.001" timestamp="2026-09-23T18:28:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="633">
			<!--Cvel 28: SMA input MS, 24 spws to combine, scratch columns, channel mode, 30 channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test29" time="0.000" timestamp="2026-09-23T18:28:42" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="650">
			<!--Cvel 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test43" time="0.001" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="972">
			<!--Cvel 43: SMA input MS, 1 spw, channel mode, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test44" time="0.001" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="990">
			<!--Cvel 44: SMA input MS, 2 spws to combine, channel mode, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test45" time="0.000" timestamp="2026-09-23T18:28:59" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1008">
			<!--Cvel 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
		<testcase classname="cvel_test" name="test47" time="0.001" timestamp="2026-09-23T18:29:01" file="/home/casatest/casa6/casatasks/tests/casashell_tests/test_task_cvel_casashell.py" line="1042">
			<!--Cvel 47: SMA input MS with descending freq, 1 spw, nchan not set-->
			<skipped type="skip" message="Skip, this produces an exception since release 4.7.2 as per CAS-9798"/>
		</testcase>
	</testsuite>
</testsuites>
